As semiconductor devices move to smaller geometries, chip level power supply voltages have also scaled downward. However, system level power supply voltages have scaled at a much slower rate than individual chip supply voltages, requiring high voltage tolerant input and output pads to limit the maximum voltages appearing across semiconductor devices on the integrated circuit that may be damaged by the high voltage signals. Special design techniques must be employed for these high voltage tolerant input/output pad circuits, since the magnitude of the high voltage signals usually exceeds maximum allowable transistor terminal potentials such as drain-to-source (V.sub.DS), drain-to-gate (V.sub.DG) and gate-to-source (V.sub.GS) of the metal oxide semiconductor field-effect transistors (MOSFETs) in a given technology.
High voltage tolerant input/output pads also have ESD protection circuits that must not operate within the normal operating range of the high voltage signals. In the past, a bipolar device, e.g. a thick field-oxide (TFO) npn device, has been used since such a bipolar device is a good dissipation element to protect against electrostatic discharges and since the voltage at which the TFO begins to conduct current is above the normal operating range of applied signals but below the potential at which damage occurs in the internal circuitry. Prior art FIG. 1 is a partial block diagram, partial schematic diagram of a TFO npn device. In FIG. 1, the TFO npn device 3 provides ESD protection by a well known phenomenon known as bipolar snapback. During bipolar snapback, a parasitic bipolar device formed by a first n+ diffusion 8 coupled to the bondpad 20 (collector) and a second n+ diffusion 7 coupled to the chip V.sub.ss 45 (emitter), where the two diffusions are separated by a TFO 6, can conduct large amounts of ESD discharge current by means of a self-biased mechanism. The self-biasing results from avalanche-breakdown at the collector/base (i.e. n+ pad to p-substrate) diffusion where avalanche-generated electron-hole pairs are created. The holes generated from this effect (I.sub.SUB) migrate through the substrate 4 and its associated resistance (labeled R.sub.SUB) towards the emitter and P+ top-substrate contact. When the product of I.sub.SUB .times.R.sub.SUB &gt;0.7V the base-emitter junction (i.e. n+ V.sub.ss to p-substrate) of the TFO npn device 3 will forward bias, thereby turning the device on. The particular collector-to-emitter voltage where this effect occurs is known as V.sub.T1. Thereafter the collector-to-emitter voltage decreases as the current increases, "snapping back" from V.sub.T1. Later, the trend reverses, causing the collector-to-emitter voltage to rise as the current also rises. Eventually, the bipolar transistor fails at another particular collector-to-emitter voltage V.sub.T2. The destructive failure current threshold associated with V.sub.T2 is I.sub.T2, beyond which, the TFO npn device 3 is permanently damaged. Thus, the useful range of current conduction for ESD protection with the TFO npn device 3 (or any other lateral bipolar device) begins at V.sub.T1 and ends at (V.sub.T2, I.sub.T2). The use of low resistivity epitaxial substrates of modern semiconductor process makes V.sub.T1 of the TFO npn device 3 too high for ESD protection. The problem with the TFO npn device is that the trigger voltage of the TFO npn device, that is, the particular collector-to-emitter voltage at which the TFO begins to conduct current, is too high for modem devices (e.g. 15V). Such a high trigger voltage may permit damage in the devices in the high voltage tolerant input/output pads before any ESD protection can occur. A need therefore exists to lower the trigger voltage of such a bipolar device so that the device "triggers" earlier, to guarantee that the input/output pad circuitry is not damaged.
A technique for lowering the trigger voltage of a lateral npn bipolar device inherent in any NMOS device is by raising the local substrate potential to thereby "substrate trigger" the device which has been shown to be effective in the publication "Substrate Triggering and Salicide Effects on ESD Performance and Protection Circuit Design in Submicron CMOS Processes", Ameraskera et al., 95 IEDM pp. 547-50, incorporated by reference herein. However, the NMOS device cannot serve as a protection element for high voltage tolerant applications since the magnitude of these high voltage signals usually exceeds the maximum allowable terminal potentials. The maximum allowable terminal potentials are usually slightly higher than the maximum allowable power supply voltages for a given technology. For example, if a given technology has a maximum power supply voltage of 3.3V, then the maximum V.sub.DS, V.sub.DG and V.sub.GS of MOSFETs in the technology may be 3.6V. It is a common requirement for integrated circuits fabricated in such a technology to be tolerant of 5V input signals. Thus, this type of chip cannot use the NMOS (and its associated parasitic npn bipolar device) as an ESD protection element. This will continue to be a limitation as technology advances since newer chips must be backward compatible with the signal levels of older chips used in the same system, and since as chip (and system) power supplies scale downwards, so will the maximum allowable terminal potentials of transistors in these technologies. Therefore, a need exists to reduce the trigger voltage of a TFO npn device or similar lateral npn device to a potential below MOSFET failure thresholds, so that it can be used to provide ESD protection for high voltage tolerant applications. A need also exists to increase the current gain (.beta.) of these devices to increase ESD robustness. Furthermore, if lateral npn devices are used, the base electrode is usually the chip substrate, which is very closely coupled to ground in modern technologies due to the use of epitaxial substrates. The close coupling to ground of the npn base is the dominant factor which increases the trigger voltage of these devices in modern technologies. Therefore, a need exists to reduce the degree of coupling to ground for the npn device, in a manner which is compatible with the semiconductor manufacturing process.